1. Field of the Invention
This invention relates generally to field emission displays (FEDs) and more particularly to a method for preventing junction leakage in FEDs.
2. State of the Art
Flat panel displays have recently been developed for visually displaying information generated by computers and other electronic devices. Typically, these displays are lighter and utilize less power than conventional cathode ray tube displays. One type of flat panel display is known as a cold cathode field emission display (FED).
A cold cathode FED uses electron emissions to illuminate a cathodoluminescent screen and generate a visual image. An individual field emission cell typically includes one or more emitter sites formed on a baseplate. The baseplate typically contains the active semiconductor devices that control electron emission from the emitter sites. The emitter sites may be formed directly on a baseplate formed of a material such as silicon or on an interlevel conductive layer (e.g., polysilicon) or interlevel insulating layer (e.g., silicon dioxide, silicon nitride) formed on the baseplate. A gate electrode structure, or grid, is typically associated with the emitter sites. The emitter sites and grid are connected to an electrical source for establishing a voltage differential to cause a Fowler-Nordheim electron emission from the emitter sites. These electrons strike a display screen having a phosphor coating. This releases the photons that illuminate the screen. A single pixel of the display screen is typically illuminated by one or several emitter sites.
In a gated FED, the grid is separated from the base by an insulating layer. This insulating layer provides support for the grid and prevents the breakdown of the voltage differential between the grid and the baseplate. Individual field emission cells are sometimes referred to as vacuum microelectronic triodes. The triode elements include the cathode (field emitter site), the anode (cathodoluminescent element) and the gate (grid). U.S. Pat. No. 5,210,472 to Stephen L. Casper and Tyler A. Lowrey entitled "Flat Panel Display In Which Low-Voltage Row and Column Address Signals Control A Much Higher Pixel Activation Voltage", describes a flat panel display that utilizes FEDs.
In flat panel displays that utilize FEDs, the quality and sharpness of an illuminated pixel site of the display screen is dependent on the precise control of the electron emission from the emitter sites that illuminate a particular pixel site. In forming a visual image, such as a number or letter, different groups of emitter sites must be cycled on or off to illuminate the appropriate pixel sites on the display screen. To form a desired image, electron emission may be initiated in the emitter sites for certain pixel sites while the adjacent pixel sites are held in an off condition. For a sharp image, it is important that those pixel sites that are required to be isolated remain in an off condition.
One factor that may cause an emitter site to emit electrons unexpectedly is the response of semiconductor junctions in the FED to photons generated by the luminescent display screen and photons present in the environment (e.g., lights, sunshine). In an FED, P/N junctions can be used to electrically isolate each pixel site and to construct row-column drive circuitry and current regulation circuitry for the pixel operation. During operation of the FED, some of the photons generated at a display screen as well as photons from the environment, may strike the semiconductor junctions on the substrate. This may affect the junctions by changing their electrical characteristics. In some cases this may cause an unwanted current to pass across the junction. This is one type of junction leakage in a FED that may adversely affect the address or activation of pixel sites and cause stray emission and a degraded image quality.
One possible situation is shown in FIG. 1. FIG. 1 illustrates a pixel site 10 of a field emission display (FED) 13 and portions of adjacent pixel sites 10' on either side. The FED 13 includes a baseplate 11 having a substrate 12 formed of a material such as single crystal P-type silicon. A plurality of emitter sites 14 are formed on an N-type conductivity region 30 of the substrate 12. The P-type substrate 12 and N-type conductivity region 30 form a P/N junction. This type of junction can be combined with other circuit elements to form electrical devices, such as FETs, for activating and regulating current flow to the pixel sites 10 and 10'.
The emitter sites 14 are adapted to emit electrons 28 that are directed at a cathodoluminescent display screen 18 coated with a phosphor material 19. A gate electrode or grid 20, separated from the substrate 12 by an insulating layer 22, surrounds each emitter site 14. Support structures 24, also referred to as spacers, are located between the baseplate 11 and the display screen 18.
An electrical source 26 establishes a voltage differential between the emitter sites 14 and the grid 20 and display screen 18. The electrons 28 from activated emitter sites 14 generate the emission of photons from the phosphor material contained in a corresponding pixel site 10 of the display screen 18. To form a particular image, it may be necessary to illuminate pixel site 10 while adjacent pixel sites 10' on either side remain dark.
A problem may occur however, when photons 32 (i.e., light) generated by a light source 33, sunlight or other environmental factors, strike the semiconductor junctions formed in the substrate 12. In addition, photons 32 from an illuminated pixel site 10 may strike the junctions formed at the N-type conductivity regions 30 on the adjacent pixel sites 10'. The photons 32 are capable of passing through the spacers 24, grid 20 and insulating layer 22 of the FED 13, because often these layers are formed of materials that are translucent to most wave lengths of light. As an example, the spacers 24 may be formed of a translucent polymide, such as kapton or silicon nitride. The insulative layer 22 may be formed of translucent silicon dioxide, silicon nitride or silicon oxynitride. The grid 20 may be formed of translucent polysilicon.
The exposure to photons from the display screen 18 and environment may change the properties of some junctions on the substrate 12 associated with the emitter sites 14. This in turn may cause current flow and initiate electron emission from the emitter sites 14 on the adjacent pixel sites 10'. The electron emission may cause the adjacent pixels sites 10' to illuminate when a dark background may be required. This will cause a degraded or blurry image. Besides isolation and activation problems, light from the environment and display screen 18 striking junctions on the substrate 12, may cause other problems in addressing and regulating current flow to the emitter sites 14 of the FED cell 13.
In experiments conducted by the inventors, junction leakage currents have been measured in the laboratory as a function of different lighting conditions at the junction. At a voltage of about 50 volts and depending on the intensity of light directed at a junction, junction leakage may be on the order of picoamps (i.e., 10.sup.-12 amps) for dark conditions to microamps (i.e., 10.sup.-6 amps) for well lit conditions. For a FED, even relatively small leakage currents (i.e., picoamps) will adversely affect the image quality. The treatise entitled "Physics of Semiconducting Devices" by S. M. Sze, copyright 1981 by John Wiley and Sons, Inc., at paragraphs 1.6.1 to 1.6.3, briefly describes the effect of photon energy on semiconductor junctions.
In the construction of screens for cathode ray tubes, screen aluminizing processes are used to form a mirror like finish on the inside surface of the screen. This layer of aluminum reflects light towards the viewer and away from the rear of the tube. In U.S. Pat. No. 3,814,968 to Nathanson et al., a similar process is utilized in a field emitter cathodes to prevent radiation emitted at the screen from being directed back onto the photocathode and emitter sites. One problem with this prior art approach is that with field emission displays (FEDs), cathode voltages are relatively low (e.g., 200 volts). However, an aluminum layer formed on the inside surface of the display screen cannot be easily penetrated by electron emitted at these low voltages. Therefore this approach is not entirely suitable in a FED for preventing junction leakage caused by screen and environment photon emission.
It is also known in the art to construct FEDs with circuit traces formed of an opaque material, such as chromium, that overlie the semiconductor junctions contained in the FED baseplate. As an example, U.S. Pat. No. 3,970,887 to Smith et al., describes such a structure (see FIG. 8). However, these circuit traces are constructed to conduct signals, and are not specifically adapted for isolating the semiconductor junctions from photon bombardment. Accordingly, most of the junction areas are left exposed to photon emission and the resultant junction leakage.
In view of the foregoing, there is a need in the art for improved methods for preventing junction leakage in FEDs. It is therefore an object of the present invention to provide an improved method of constructing a FED with a light blocking element that prevents photons generated in the environment and by a display screen of the FED from effecting semiconductor junctions on a baseplate of the FED. It is a still further object of the present invention to provide an improved method of constructing FEDs using an opaque layer that protects semiconductor junctions on a baseplate from light and which may also perform other circuit functions. It is a still further object of the present invention to provide a FED with improved junction leakage characteristics using techniques that are compatible with large scale semiconductor manufacture.